The present invention generally relates to semiconductor memory devices and more particularly to a semiconductor memory device having a redundant construction.
With increasing storage capacity of semiconductor memory devices, fabrication of memory devices which are entirely free from the defective memory cell is becoming increasingly difficult. Particularly, in the case of the memory cells fabricated with a newly developed process, there is a tendency that a number of defects are involved. When the memory devices which contain defect are rejected entirely, the yield of production of the memory device is seriously decreased.
In order to avoid such a problem and use the memory devices which contain defective memory cells, it is generally practiced to use a redundant construction wherein redundant memory cell columns are provided in the memory cell array. In use, a map of defective memory cells in the memory cell array is stored in a read-only memory and the like and the address signal addressing the defective memory cell in the array is converted, on the basis of the map, to an address signal which addresses a normal, defect-free memory cell. More specifically, when there is an address signal addressing a defective memory cell, the memory cell column including the defective memory cell column is switched to another, redundant memory cell column. Thereby, a normal memory cell is used in place of the addressed defective memory cell and the memory device operates as if it is a defect-free device.
Meanwhile, there is known a construction of memory device wherein the memory cell array are divided into a number of blocks each containing a number of memory cells arranged in a row and column formation. In each of the blocks, a memory cell is connected to a bit line and a divided word line which is a word line branched from a main word line.
FIG. 1 shows such a conventional semiconductor memory device having the divided word line construction.
Referring to FIG. 1, the memory cell array 1 is divided into a number of blocks or memory cell columns 2, 3, 4, . . . each containing a number of memory cells 15, 16, 17, . . . arranged therein in a row and column formation.
Commonly to the blocks 2-4, a number of word line drivers 19 each connected to a main word line MWL are provided, wherein only one word line driver 19 is illustrated in the drawing. The main word line MWL extends throughout the memory cell array 1, passing through the blocks 2-4. The word line driver 19 is supplied with a word line selection signal addressing one of the main word lines MWL from an X-decoder 24 along a bus 24a, in response to address data ADDRESS1 supplied to the X-decoder 24.
Further, there is provided a Y-decoder 25 to which a second address data ADDRESS2 is supplied, wherein the Y-decoder 25 is connected to bit line drivers 11, 12, 13, . . . via an address bus 25a for selectively addressing a pair of bit lines BL and BL via respective read/write controllers 6, 7, 8, . . . . Thus, when the address data ADDRESS1 and ADDRESS2 which address together the memory cell 15 in the block 2 has come in to the decoders 24 and 25, the bit line decoder 11 energizes the controller 6 in response to the output of the Y-decoder 25, and thereby the bit line BL and BL connected to the addressed memory cell 15 are selected. At the same time, the main word line driver 19 is energized in response to the output of the X-decoder 24 and the main word line driver 19 selects the main word line MWL connected thereto.
In the foregoing memory cell device of the divided word line construction, there is provided a gate device 20 which is supplied with the output of the main word line driver 19 and the output of the bit line driver 11 for producing an output which is supplied to the memory cell 15 via a divided word line DWL. Thus, only when the block 2 is addressed in response to the output of the bit line driver 11 of the block 2 and at the same time by the word line MWL which is addressed in response to the output of the main word line driver 19, the gate device 20 is energized and the divided word line DWL connected to the addressed memory cell 15 is selected. In the illustrated example, the bit line driver 11 and the main word line driver -9 are constructed as a NAND gate while the gate device 20 is constructed as a NOR gate. Thus, the divided word line DWL is selected in response to the low level output of the devices 11 and 19. An exactly the same construction is provided also in other blocks.
When reading data stored in the memory cell such as the memory cell 15 in the memory cell array 1, the data in the memory cell 15 is transferred along the bit lines BL and BL to the controller such as the controller 5, and from there transferred further to a sense amplifier 10a along a read bus 26. When writing data, on the other hand, the data supplied to a data input terminal DIN is transferred to to the selected controller such as the controller 6 along a write bus 27 after amplification in a write amplifier 10b, and the data is further transferred to the memory cell such as the memory cell 15 along the bit lines BL and BL.
By adopting the divided word line construction in combination of the block construction of the memory cell array, the length of the word line connected to the memory cell can be reduced and thereby the access time of the memory device is significantly reduced as a result of the reduction of parasitic capacitance associated with the memory cells connected to the word line.
In such a memory device having the divided word line construction, too, the foregoing redundant construction is employed. In this case, the redundant memory cells are provided in each of the blocks 2-4 and operation of the bit line driver is controlled such that an alternative bit line or memory cell column is selected when a bit line which is connected to one or more defective memory cells is addressed. For this purpose, a read-only memory not illustrated is provided in cooperation with each of the bit line drivers 11-13.
In such a conventional memory device having the divided bit line construction and the redundant construction, there is a problem, associated with the fact that the selection of the alternative memory cell column can only be made within a same block of the memory cell array, that the redundant memory cell column or columns have to be provided in each of the blocks and thus, the proportion of the memory cells used for the redundancy purpose tends to become excessively large. In other words, there is a problem that the chip size of the memory device tends to become excessively large due to the redundant construction.